A conventional DRAM is organized in a matrix-structure having a predetermined number of rows and columns per memory bank. By selecting a row (providing a row-address) the memory elements of all columns associated to the selected row are readable, as all memory elements (capacitors) associated to the row are connected to the data lines (columns).
In order to allow for a reliable readout, the data-lines (column-lines) have to be precharged prior to the connection of the storage capacitors to the column-lines. Precharging is performed by applying a predetermined voltage which is chosen between the high- and the low-voltage of the system to each individual column-line. Even when the voltage source is disconnected from the column-lines, the voltage is maintained for a certain amount of time, due to the capacitance of the column-lines. It is only possible to reliably sense the small voltage variations caused by the charge stored on the individual storage capacitors, when the column-lines had been precharged. However, precharging takes a certain amount of time, which is called row-precharge time tRP, and which is usually expressed in terms of clock cycles. Once the signal on the column lines has stabilized, a specific column may be chosen by a column address. After the column address and the associated sense amplifiers on the column (word)-lines have stabilized, data is provided at the output of the memory element. Often, more than one single bit is provided as a result of a read-request (a single read-command). Then, the transmission of data (the so-called burst length) might take longer than one single clock single.
Memory arrays are furthermore organized in larger entities, so-called banks, which can be selected individually by a memory controller. That is, different banks exist, each bank having associated rows and columns of memory elements. As an even larger entity, ranks might exist, each rank having a plurality of memory banks, and each memory bank having a plurality of rows.
That is, to physically access a specific memory element, a rank has to be chosen, a bank within the rank has to be selected and within the bank, the desired row and column has to be accessed.
Access time of modern DRAMs depend on previous accesses and, in particular, on the location of the memory cells within the physical memory-arrangement of the DRAMs as it is illustrated in FIG. 1.
FIG. 1 shows three different scenarios a), b) and c) of two consecutive memory read operations with significantly differing response times, i.e., with completely different times that elapse from the first memory read request until the delivery of the data of the following read request.
FIG. 1a illustrates the best-case scenario, in which two consecutive memory accesses are performed to the same row of the same bank of a memory module. FIG. 1b illustrates the worst-case, where consecutive memory accessed are scheduled to different rows of the same memory-bank. FIG. 1c shows a scenario, where consecutive memory accesses are performed to different banks of a memory module.
The selection of the different ranks, banks and rows/columns is performed by an associated memory controller. The example in FIG. 1 does, for the sake of simplicity, assume that there exists only one rank, such that only bank select signals will be discussed in the following paragraphs.
FIG. 1a illustrates the access-timing of two consecutive memory accesses to different columns of the same row of the same bank. In the timing diagrams subsequently discussed, the first row 2 schematically illustrates the clock signal. On occurrence of the clock signal 2, the commands or data provided at a command line 4 and an address line 6 are evaluated and the corresponding operation is performed. The provision of data read out at the data lines 8 is also synchronized with the clock signal, as it is common practice. The commands or operations performed by a memory controller when accessing the memory are indicated in the command line 4, whereas the address line 6 illustrates the addresses (bank, row and column addresses) that are intended to be accessed. The data row 8 does schematically sketch the data provided and the latency, i.e., the time elapsed after the issue of the read command until the first data bit is provided by the memory.
When consecutively accessing two different columns within the same row of the same bank, a continuous data stream of two data bursts can be retrieved after an unavoidable read latency occurring after the first read command. In particular, the memory bank comprising the memory element to be accessed has to be activated first. For that purpose, the bank address and the row address are provided at the address lines 6 in step 10a, simultaneous to an activate command, which is send on the command line 4, indicating that the corresponding bank shall be used and activated.
It may be noted that, for the ease of understanding, the times which are required for the stabilization of the address signals and of the read-out signals at the column lines are subsequently omitted to focus only on those timings that can be improved by accessing different memory elements. This is fully justified as inherent electrical properties of the bit lines, i.e., the capacitants and so on, cannot be influenced by different access schedules, which shall be discussed here. Therefore, the timing diagram of FIG. 1a is based on the assumption that the row of the associated bank is selected and that the signals of the associated memory elements are available at the column lines one clock cycle after the activation command.
In the following clock cycle 10b, the column address can be provided at the address lines together with the bank address, whereas the command line indicates that a read operation is to be performed (a read request). After the read request, the so-called “read latency” is required until the data burst is available at the data lines of the memory module, which is the case at clock cycle 12 in the given example. With the end of the data burst at clock cycle 14, the first read operation is finished.
As the second, consecutive memory access is performed to a different column in the same row of the same bank, the next column address to be read out can be provided on address line 16 without selecting a different bank. However, the next read operation can only be requested after the expiration of the burst length 18, which is considered by the memory controller. After the burst length 18, the next column address 16 is issued together with a read command and, as no further latencies have to be considered, the requested burst of data will be provided right after the first data burst of the first read request 10b. 
FIG. 1b illustrates the timing, when consecutive memory accesses are performed to the same memory bank, but to different rows within the bank. As the command sequence for the first memory access equals the command sequence of the previously described memory access, a repeated description of the first two steps 10a and 10b will be omitted.
Generally, identical or like elements or steps will be assigned the same reference numerals throughout the application and a repeated description of those elements will be omitted.
As the second memory access accesses a different row of the same memory bank, the second read command cannot be issued as quickly as in FIG. 1a. Instead, all columns of the respective bank have to be precharged before the next row-selection can be performed. That is, a precharge command has to be issued at step 20 to trigger a precharge of the column-lines of the associated memory banks. There is a certain minimum time (row access strobe) that has to be waited after an activate command to the following precharge command. Therefore, an additional latency (tRAS) occurs, when two rows of memory shall be consecutively accessed within the same memory bank.
Furthermore, precharging itself requires a certain, even larger, amount of time (tRP), the row-precharge time 24. That is, the next activate signal can only be issued in step 26, which can then be followed by the second read request 28. The second read request can therefore only be issued after the first read request when the latencies of tRAS 22 and tRP 24 (the so-called “row cycle” time tRC) are elapsed. That is, in other words, once two consecutive memory accesses access the same row within the same memory bank of a DRAM, large additional, undesirable latencies have to be accepted, which significantly decrease the memory performance and the overall memory bandwidth.
FIG. 1c illustrates the timing when accessing different rows of different banks. Therefore, in a step 30, which follows step 10b of the previous read request, the new bank address and the associated row address can be provided at the address lines and the corresponding activate command can be sent. After the activation of the new bank (BkK), the second read request can be directly issued, associated by the column address of the column to be read out. The first burst of data is received after the read latency, as in the previous cases. However, the second burst of data 34 from the second memory bank is received after only a short delay time, as illustrated in FIG. 1c. 
As the previously described examples have shown, consecutive memory accesses may be performed to memory locations which deliver the requested data with a low latency or to memory locations which deliver the data with a high latency. In the most general terms, consecutive memory access to memory locations which are physically interrelated in an unfortunate way (resulting in high access times), are called memory conflicts.
The avoidance of memory conflicts may, therefore, increase the overall performance of the memory subsystem and the memory bandwidth.